1. Field of the Invention
The present disclosure generally relates to nitride semiconductor transistor devices and, more particularly, to field-effect transistors where a conductive channel beneath a gate electrode is practically switched off without gate voltage being applied on the gate electrode. In other words, it relates to normally-off type transistor devices of a nitride semiconductor transistor.
2. Description of the Related Art
GaN, AlN, and InN which are nitride semiconductors or semiconductors of mixed crystal of those nitride semiconductors, may have a wide band gap and a high mobility of conduction electrons and, thus, may be suitable for high-voltage high-output electron devices. In particular, the operation of a low on-resistance with a large current under high-voltage is possible in field-effect transistors (FETs) formed of nitride semiconductors and one of those embodiments. That is, in a high electron mobility transistor (HEMT), conduction electrons induced at the interface of a semiconductor heterojunction of AlGaN/GaN, etc., transport through a conductive channel. Thereby, those FETs and HEMTs have been used for high-output power amplifiers and/or high-power switching devices.
However, in usual nitride semiconductor FETs, the conductive channel beneath the gate electrode is in an on-state with no voltage being applied to the gate electrode. Accordingly, those FETs are normally-on. In the case that those normally-on switching devices are used in power supply apparatuses, the switch is opened while the control voltage to be applied to the gate electrode is lost due to an unknown error operation, etc. This may cause the system to be totally broken. Therefore, the normally-on FET is decisively unsuitable for the high-power switching devices to be used in a power supply from the viewpoint of safety.
For this reason, several technologies to make nitride semiconductor FETs normally-off have been developed. As an example among them, it is known that a p-type nitride semiconductor layer inserted beneath the gate of FET to form a PN junction type gate electrode can provide a normally-off operation. (See Y. Uemoto et al., IEEE Transactions on Electron Devices Volume 54,Number 12, December 2007, p. 3393.) In this technology, the operation range of a gate voltage is limited to the flat band voltage determined by the semiconductor band gap. Thereby, any positive threshold voltage must be less than 2 V, which is insufficient because the positive threshold voltage is required to be more than 3V in usual power-supply apparatuses. Moreover, a positive voltage to be applied to the gate electrode is limited by the on-voltage of the PN junction. The small gate voltage amplitude limits the magnitude of the electric current flowing through the conductive channel in the on-state of FET.
In another method to achieve the normally-off FET, an insulating film is inserted beneath the gate of the FET to form a Metal-Insulator-Semiconductor (MIS) junction gate electrode. (See M. Kanamura et al., IEEE Electron Device Letters, Volume 31, Number 3, March 2010, p.189.) Since there is the insulator beneath the gate metal in this method, the leakage current flowing through the gate electrode is suppressed, which enables the device operation at a large positive gate voltage. Thus, the amplitude range of the gate voltage is able to be wide enough even for a large positive threshold voltage, compared with the PN junction type gate electrode.
FIG. 7 is a drawing illustrating the cross-sectional structure of main parts of GaN FET having the conventional MIS-type gate electrode. The material of the substrate 1001 may be Silicon-carbide (SiC), Silicon (Si), Sapphire, GaN and so forth. The buffer layer 1002, the GaN layer 1003, and the AlGaN layer 1004 are in turn formed by the epitaxial growth and layered on this substrate 1001. The AlGaN layer 1004 below the gate electrode is partially removed by the recess etching process. The gate electrode 1007 is formed by inserting the insulating film 1005 in the recess etching portion 1006. Subsequently, the source electrode 1008 and the drain electrode 1009 are formed to complete the main parts of the GaN HEMT. The material for the insulating film 1005 may be, for example, aluminum oxide, silicon oxide, silicon nitride, or other hitherto known gate insulating materials. The conduction electrons are induced on the side of GaN layer 1003 at the interface between the GaN layer 1003 and the AlGaN layer 1004 having a wider band gap than the GaN layer 1003. Thus, the conductive channel 1010 is formed. The conduction electron density in the conductive channel 1010 directly beneath the gate electrode 1007 is controlled by the voltage to be applied to the gate electrode 1007. Then, transistor operation may be obtained. This conventional FET uses the conductive channel formed at the interface of an AIGaN/GaN semiconductor hetero structure, and is called HEMT as one of FETs.
FIG. 8 is a drawing illustrating the cross-sectional structure of a main part of a GaN FET having another type of the conventional MIS gate electrode. Similar to the illustration in FIG. 7, the material for the substrate 1101 may be Silicon-carbide (SiC), Silicon (Si), Sapphire, GaN and so forth. The buffer layer 1102, the GaN layer 1103, and the AlGaN layer 1104 are in turn formed by the epitaxial growth and layered on the substrate 1101. Moreover, the material for the insulating film 1105 may be, for example, aluminum oxide, silicon oxide, silicon nitride, or other hitherto known gate insulating materials. Different from the illustration in FIG. 7, the recess etching portion 1106 is deeper, and its bottom portion goes through the AlGaN layer 1104 to reach the GaN layer 1103. The conductive channels 1101 formed at the interface of AlGaN/GaN are respectively spread on both sides of the gate electrode 1007, and electrically connect between the source electrode 1108 and the gate electrode 1107, and between the drain electrode 1109 and the gate electrode 1107. The conductive channel 1111 directly beneath the gate electrode 1107 is formed by conduction electrons induced at the interface between the insulating film 1105 and the GaN layer 1103. The density of those conduction electrons is controlled by the voltage to be applied to the gate electrode 1107, and the transistor operation may be obtained.